1. Technical Field
The present disclosure is related to a memory device, and in particular to, a memory test system and method for testing the memory device.
2. Description of Related Art
Currently, the memory device technology develops fast, and the memory devices with large capacities are usually used in our daily life. The memory device may have many configurations for allocating the memory banks in the memory devices, such as a 16M×4, an 8M×8, a 16M×16, and the other configurations. In the a×4 configuration, four input/output pins are wired to four external electrical leads, wherein a is the capacities of the memory bank. In the a×8 configuration, eight input/output pins are wired to four external electrical leads. The configuration of the memory device can determine the performance, speed, and test time of the memory device.
Compared to the memory device using the a×4 configuration, the memory device using the a×8 configuration has four more input/output pins. Therefore, when the capacities of memory banks of the memory devices using the a×8 and a×4 configurations are the same, the speed of the memory device using the a×8 configuration is faster than that of the memory device using the a×4 configuration, and the test time of the memory device using the a×8 configuration is less than that of the memory device using the a×4 configuration. It is noted that the test time is closely tied to capacities of the memory device, and because the memory devices may have different configurations, it can be difficult to test the memory devices using different configurations efficiently.
Referring to FIG. 1, FIG. 1 is a block diagram showing a conventional memory test system. The conventional memory test system 1 comprises a memory device 10, a probe card 11, and a tester 12. The memory device 10 comprises a memory die 100, N input circuits 101_1 through 101_N, and N output circuits 102_1 through 102_N, wherein N is a number of the memory banks associated with the memory die 100. The memory die 100 has N memory banks, and the N memory banks are respectively electrically connected to N input/output pins IO_1 through IO_N of the N input circuits 101_1 through 101_N. The N output pins of the N input circuits 101_1 through 101_N are respectively electrically connected N input pins of the N output circuits 102_1 through 102_N. The N output pins of the output circuits 102_1 through 102_N are respectively electrically connected to N input pins of the probe card 11, and the N output pins of the probe card 11 are respectively electrically connected to N input pins of the tester 12.
The input circuits 101_1 through 101_N can be the input/output buffers of the memory device 10 for buffering N patches of input/output data, and the output circuits 102_1 through 102_N can be the off-chip drivers (OCD) for adjusting the N output impedances observed from the N output pins of the input circuits 101_1 through 101_N. During a test procedure, N test signals are input to and stored in the memory cells of the N memory banks, and the input circuits 101_1 through 101_N read the N test signals stored in the memory cells of the N memory banks, and outputs the N test signals to the output circuits 102_1 through 102_N. The output circuits 102_1 through 102_N outputs N output signals according to the N test signals respectively, and the N output signals are then received by the probe card 11, and the probe card 11 outputs the N output signals to the tester 12, such that the tester 12 can test whether the N output signals received by the tester 12 are matched to the N test signals originally input to the memory cells of the N memory banks.
A weak OCD is required in the low power consumption memory device 10 (such as dynamic random access memory, DRAM) which can perform less power consumption. However, the tester 12 actually has the heavy load (large impedance) in the wafer level test procedure. To perform chip-package test, too weak OCD is conflicted and not allowed.
For example, the client may merely need the 5 mA signal to drive the components outside the memory device 10, and a 40 mA signal is used to drive the tester 12. If the OCD outputs an output signal of 40 mA, it is obvious that the output current is too high. If the OCD outputs an output signal of 5 mA, it is obvious that the output current cannot drive the tester 12 in the test procedure.